The present invention relates to a semiconductor device fabrication method, more specifically a semiconductor device fabrication method in which silicidation is made by using nickel.
As a technique for making gate electrodes and source/drain diffused layers low resistive, the so-called SALICIDE (Self-Aligned Silicide) process is known.
In the SALICIDE process, as a metal material to be reacted with silicon, cobalt (Co) is dominantly used (refer to Patent Reference 1).
Recently, as semiconductor devices are increasingly micronized, the gate length tends to be much shorter.
In siliciding gate electrodes of a very short gate length with cobalt film, the phenomena that the scatter of a resistance of the gate electrodes is abruptly increase has been confirmed.
Nickel silicide is much noted for the merit that, when the gate length of gate electrodes is very short, nickel silicide makes the resistance scatter of the gate electrodes very small in contrast to such cobalt silicide.
On the other hand, the mobility of carriers (holes) of PMOS transistors is lower than that of carriers (electrons) of NMOS transistors. When PMOS transistors are simply formed, often the PMOS transistors cannot have sufficiently high operation speed.
Then, a technique that a silicon germanium layer (Si1-xGex layer) is buried in the source/drain regions of the PMOS transistors to apply compression strain to the channel regions of the PMOS transistors, whereby the mobility of the carriers (holes) in the PMOS transistors is improved to improve the operation speed of the PMOS transistors is proposed (refer to Patent Reference 2).
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. Hei 9-251967
[Patent Reference 2]
Specification of U.S. Pat. No. 6,621,131
[Patent Reference 3]
Specification of Japanese Patent Application Unexamined Publication No. 2002-237466
[Patent Reference 4]
Specification of Japanese Patent Application Unexamined Publication No. 2001-53027
[Non-Patent Reference 1]
J. Seger et al., “Morphological instability of NiSi1-uGeu on single-crystal and polycrystalline Si1-xGex”, J. Appl. Phys., Vol. 96, No. 4, pp. 1919-1928 (2004)
[Non-Patent Reference 2]
Anne Lauwers et al., “Materials aspects, electrical performance, and scalability of Ni silicide towards sub-0.13 μm technologies”, J. Vac. Sci. Technol., B, Vol. 19, No. 6, pp. 2026-2037 (2001)
As semiconductor devices are increasingly micronized and integrated, the junction depth of the source/drain diffused layers becomes smaller. The nickel silicide film must be formed much thinner. When the silicide film is formed thick, the electric field between the junctions of the source/drain diffused layer and the silicide film becomes stronger, which increases the junction leak current.
However, when thin nickel film is simply used to silicide the silicon germanium layer, often the sheet resistance is increased. When thin nickel film is simply used to silicide the silicon germanium layer, Ni(Si1-xGex)2 crystals are formed in spikes below the silicide film down to the vicinity of the junctions of the source/drain diffused layer, which often increases the junction leak current.